AI & ChatGPT searches , social queriess for PROCESSOR REGISTER
Search references for PROCESSOR REGISTER. Phrases containing PROCESSOR REGISTER
See searches and references containing PROCESSOR REGISTER!
Search references for PROCESSOR REGISTER. Phrases containing PROCESSOR REGISTER
See searches and references containing PROCESSOR REGISTER!PROCESSOR REGISTER
Quickly accessible working storage available as part of a digital processor
A processor register is a quickly accessible storage location available to a computer's processor. Registers usually consist of a small amount of fast
Processor_register
Topics referred to by the same term
a collection of bits Processor register, a component inside a central processing unit for storing information Quantum register, the quantum mechanical
Register
Central computer component that executes instructions
A central processing unit (CPU), also known as a central processor, main processor, or simply processor, is the primary processor in a given computer
Central_processing_unit
Processor register which changes or controls the general behavior of a CPU
A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control
Control_register
Register in a computer's CPU
memory location specified by the memory address register. It acts as a buffer, allowing the processor and memory units to act independently without being
Memory_buffer_register
Component of a computer's processor
A stack register, also known as a stack pointer, is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based
Stack_register
CPU register containing flags
state of the processor. Individual bits are implicitly or explicitly read or written by the machine code instructions executing on the processor. The status
Status_register
Parallel processing technique
a register (SWAR), also known by the name "packed SIMD" is a technique for performing parallel operations on data contained in a processor register. SIMD
SWAR
Family of instruction set architectures
be orders of magnitude worse than on a true x86 processor. The market rejected the Itanium processor since it broke backward compatibility and preferred
X86
Combinational digital circuit
depend on the architecture of the encapsulating processor and the operation being performed. Processor architectures vary widely, but in general-purpose
Arithmetic_logic_unit
Computer processor which works on arrays of several numbers at once
In computing, a vector processor is a central processing unit (CPU) that implements an instruction set where its instructions are designed to operate
Vector_processor
Working storage in a computer processor
convey the register's output value. Register files are used in a variety of applications, including as processor registers in central processing units (CPUs)
Register_file
Computer component
main memory, and the processor can retrieve the frame number from the page-table entry to form the physical address. The processor also updates the TLB
Translation_lookaside_buffer
CPU that implements instruction-level parallelism within a single processor
processor (or multiple-issue processor) is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor
Superscalar_processor
CPU register used for modifying operand addresses
An index register in a computer's CPU is a processor register (or an assigned memory location) used for pointing to operand addresses during the run of
Index_register
Computer hardware technology
contrast to the normal processor initialization [which involved the boot-strap-processor (BSP) sending a Start-up Inter-Processor Interrupt (SIPI) to each
Trusted_Execution_Technology
System comprising multiple qubits
computing, a quantum register is a system comprising multiple qubits. It is the quantum analogue of the classical processor register. Quantum computers
Quantum_register
CPU register that is always zero
A zero register is a processor register that always returns the value zero and has no effect when it is written to. It is found in instruction set architectures
Zero_register
Data structure that maps one or more adjacent bits
state. As an example, the status register of the 6502 processor is shown below: These bits are set by the processor following the result of an operation
Bit_field
Structure on x86-based computers that holds information about a task
management. Specifically, the following information is stored in the TSS: Processor register state I/O port permissions Inner-privilege level stack pointers Previous
Task_state_segment
Problems with central processing unit design
the processor has been cleared of all instructions and can proceed free from hazards. All forms of stalling introduce a delay before the processor can
Hazard (computer architecture)
Hazard_(computer_architecture)
Microprocessor
successor, the "Hobbit" C-language Reduced Instruction Set Processor (CRISP). The Bellmac 32 processor was developed by AT&T engineers in three different Bell
Bellmac_32
Computer architecture bit width
Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data
64-bit_computing
Hardware cache of a central processing unit
location in the memory, the processor checks whether the data from that location is already in the cache. If so, the processor will read from or write to
CPU_cache
Instructions directly executable by a computer
Loop control Input/output On processor architectures with variable-length instruction sets (such as Intel's x86 processor family) it is, within the limits
Machine_code
Microcontroller machine language
the processor register file (so I/O ports begin at RAM address 0) and expanding the I/O port range. Now the first 4K is special function registers, the
Atmel_AVR_instruction_set
Multi-core microprocessor microarchitecture
the Cell processor can be split into four components: external input and output structures, the main processor called the Power Processing Element (PPE)
Cell_(processor)
Method of CPU communication
execution CPU vulnerabilities A memory that besides registers is directly accessible by the processor, e.g. DRAM in IBM PC compatible computers or Flash/SRAM
Memory-mapped I/O and port-mapped I/O
Memory-mapped_I/O_and_port-mapped_I/O
Register in a CPU control unit holding the currently-executing instruction
retrieving the operands from memory, allocating processor resources to execute the command (in super scalar processors), etc. The output of the IR is available
Instruction_register
Sequence of program instructions invokable by other software
designated register. The branch instructions BAL or BALR, designed for procedure calling, would save the return address in a processor register specified
Function (computer programming)
Function_(computer_programming)
Datum of integral data type
computers. Computer hardware nearly always provides a way to represent a processor register or memory address as an integer. The value of an item with an integral
Integer_(computer_science)
Computer compiler optimization technique
register allocation is the process of assigning local automatic variables and expression results to a limited number of processor registers. Register
Register_allocation
64-bit extension of the ARM architecture
key characteristics of the processor’s environment. This includes the number of bits used in the primary processor registers, the supported instruction
AArch64
36-bit computer by Digital (1966–1983)
main processor, which is typically booted from the same RP06 disk drive as the PDP-11. The PDP-11 performs watchdog functions once the main processor is
PDP-10
Family of four-bit digital ICs
Am2901 chip included an arithmetic logic unit (ALU) and 16 4-bit processor register slices, and was the "core" of the series. It could count using 4 bits
AMD_Am2900
Security-related instruction code processor extension
J5005 Processor". Retrieved 2020-07-10. "11th Generation Intel Core Processor Datasheet". Retrieved 2022-01-15. "12th Generation Intel Core Processors Datasheet"
Software_Guard_Extensions
CPU for the GameCube
existing PowerPC 750CXe processor to suit Nintendo's needs, such as tight and balanced operation alongside the "Flipper" graphics processor. The customization
Gekko_(processor)
Technique that abstracts logical registers from physical registers
particular logical register, the processor transposes this name to one specific physical register on the fly. The physical registers are opaque and cannot
Register_renaming
16-bit microprocessor
the 8086 processor". — (June 2020). "Die shrink: How Intel scaled down the 8086 processor". — (July 2020). "The Intel 8086 processor's registers: from chip
Intel_8086
8-bit microprocessor
microprocessor families. One of the bits in the processor state word (see below) indicates that the processor is accessing data from the stack. Using this
Intel_8080
Instruction set designed by Intel
earlier the Intel i750 video pixel processor. MMX is a processor supplementary capability that is supported on IA-32 processors by Intel and other vendors as
MMX_(instruction_set)
Component of computer engineering
a processor as seen by an assembly language programmer or compiler writer. The ISA includes the instructions, execution model, processor registers, address
Microarchitecture
RISC instruction set architecture
include a co-processor (CP) that performs co-processor-specific operations; the architecture does not specify what functions a co-processor would perform
SPARC
Digital circuit that produces sums from inputs
and other kinds of processors, adders are used in the arithmetic logic units (ALUs). They are also used in other parts of the processor, where they are used
Adder_(electronics)
Low-level parallel thread execution virtual machine and instruction set architecture
determined by its compute capability. PTX uses an arbitrarily large processor register set; the output from the compiler is almost pure static single-assignment
Parallel_Thread_Execution
Processor executing one instruction in minimal clock cycles
by using RISC microprocessors. The varieties of RISC processor design include the ARC processor, the DEC Alpha, the AMD Am29000, the ARM architecture
Reduced instruction set computer
Reduced_instruction_set_computer
Series of systems-on-a-chip designed by Apple
without the system's knowledge by using an unintentionally writable processor register as a covert channel, violating the security model and constituting
Apple_M1
Instructions for the x86 microprocessors
Knights Landing co-processor, which shipped in 2016. In conventional processors, AVX-512 was introduced with Skylake server and HEDT processors in 2017. AVX
Advanced_Vector_Extensions
Task of creating a processor
Processor design is a subfield of computer engineering and electronics that deals with creating a processor, a key component of computer hardware. While
Processor_design
32-bit microprocessor by Intel
originally released as the 80386 and later renamed i386, is the first 32-bit processor in the line, marking it a significant evolution in the x86 microarchitecture
I386
Topics referred to by the same term
CPUs DXing, in amateur radio and broadcasting DX register, a 16-bit general-purpose X86 processor register Digital transformation, the use of new digital
DX
Type of computer
of a hardware processor, a hardware stack is used. The use of a stack significantly reduces the required number of processor registers. Stack machines
Stack_machine
Term in computer security
the processor checks if the return address stored in the normal stack and shadow stack are equal. If the addresses are not equal, the processor generates
Control-flow_integrity
Topics referred to by the same term
Instruction pointer, a processor register Intelligent Peripheral, a part of a public telecommunications Intelligent Network Image processing ip, a Linux command
IP
in which transfer of information occurs are: Memory-location Processor Register Registers in I/O device V. Heuring, H. Jordan (1997). Ch 2 RTN. v t e
Register_transfer_notation
Calculations where numbers' precision is only limited by computer memory
storing values as a fixed number of bits related to the size of the processor register, these implementations typically use variable-length arrays of digits
Arbitrary-precision arithmetic
Arbitrary-precision_arithmetic
Computing paradigm to improve computational efficiency
high-performance central processing units (CPUs) to make use of instruction cycles that would otherwise be wasted. In this paradigm, a processor executes instructions
Out-of-order_execution
Processors using some version of the MIPS architecture
instructions were added to retrieve the results from this unit back to the processor register file; these result-retrieving instructions were interlocked. The R2000
MIPS_architecture_processors
Status register of x86 architecture
did not persist, the processor is earlier than the 486. Starting with the Intel Pentium, the CPUID instruction reports the processor model. However, the
FLAGS_register
pipelining, in which the processor works on multiple instructions in different stages of completion. For example, the processor can retrieve the operands
History of general-purpose CPUs
History_of_general-purpose_CPUs
Family of 1960s mainframe computers
from these programs are read into the central processor registers and are executed by the central processor at scheduled intervals. The results are then
CDC_6000_series
Circuit components acting like computer memory
registers include: The registers in a central processing unit (CPU), which are called processor registers configuration and start-up of certain features
Hardware_register
8-bit microprocessor from 1975
maskable hardware interrupt occurs when the processor is fetching a BRK instruction, the NMOS version of the processor will fail to execute BRK and instead proceed
MOS_Technology_6502
Basic unit of quantum information
completely in either one of its two states, and a set of n bits (e.g. a processor register or some bit array) can only hold a single of its 2n possible states
Qubit
64-bit extension of x86 architecture
registers. Legacy mode is the mode that the processor is in when it is not in long mode. In this mode, the processor acts like an older x86 processor
X86-64
Act of overwriting a resource
clobbering is the act of overwriting a resource such as a file, processor register or a region of memory, such that its content is lost. Generally, the
Clobbering
Microprocessor
microcontrollers. In 1989, Motorola introduced the 68302 communications processor. This processor was formerly supplied by Freescale and NXP after Motorola spun
Motorola_68000
Open-source CPU instruction set architecture
core, the U8 Series Processor IP. SiFive was established specifically for developing RISC-V hardware and began releasing processor models in 2017. These
RISC-V
64-bit x86 register
processor clock cycle is determined by the current core-clock to busclock ratio. Intel SpeedStep technology transitions may also impact the processor
Time_Stamp_Counter
Canceled SPARC microprocessor
The Rock processor implements the 64-bit SPARC V9 instruction set and the VIS 3.0 SIMD multimedia instruction set extension. Each Rock processor has 16
Rock_(processor)
call or jump such as "CALL EBX" or "JMP ESP", where the appropriate processor register was previously prepared by the exploit to point to where the payload
Register_spring
Family of RISC-based computer architectures
of the era generally shared memory between the processor and the framebuffer, which allowed the processor to quickly update the contents of the screen without
Arm_architecture_family
Control registers in some x86 processors
the 80386 processor, Intel began introducing "experimental" features that would not necessarily be present in future versions of the processor. The first
Model-specific_register
Intel microprocessor
Pentium processor and its features: Pentium Processor Family Developer's Manual Pentium Processor (Volume 1) (Intel order number 241428) Pentium Processor Family
Pentium_(original)
Topics referred to by the same term
data retrieval Index mapping of raw data for an array Index register, a processor register used for modifying operand addresses during the run of a program
Index
Register that stores where in a program a processor is executing
A program counter (PC) is a register that stores where a computer program is being executed by a processor. It is also commonly called the instruction
Program_counter
Topics referred to by the same term
block ciphers EAX register, a 32-bit processor register of x86 CPUs Environmental Audio Extensions, a number of digital signal processing presets for audio
EAX
Topics referred to by the same term
Accumulator (bet), a parlay bet Accumulator (computing), in a CPU, a processor register for storing intermediate results Accumulator (computer vision), discrete
Accumulator
32-bit version of x86 architecture
19, 2014. The Intel386 processor was the first 32-bit processor in the IA-32 architecture family. It introduced 32-bit registers for use both to hold operands
IA-32
32-bit CPU for the Wii
90 nm SOI process and later produced with a 65 nm SOI process. According to IBM, the processor consumes 20% less power than its predecessor, the 180 nm
Broadway_(processor)
Topics referred to by the same term
italiana, a Swiss radio and television broadcaster RSI register, a 64-bit processor register of x86 CPUs Recursive self-improvement, a concept in artificial
RSI
Instruction set architecture developed by Digital Equipment Corporation
programs more direct access to the register. SPL (set priority level) MTPS (move to Processor Status) MFPS (move from Processor Status) On PDP-11s that provide
PDP-11_architecture
Internal representation of numeric values in a digital computer
calculations are carried out with number formats that fit into a processor register, but some software systems allow representation of arbitrarily large
Computer_number_format
Compact format of microprocessor instructions
processor registers can be used. The concept was originally introduced by Hitachi as a way to improve the code density of their SuperH RISC processor
Compressed_instruction_set
Classification of computer architectures
ASP associative array SIMT processor predates NVIDIA by 20 years. There is some difficulty in classifying this processor according to Flynn's taxonomy
Flynn's_taxonomy
Computer processor contained on an integrated-circuit chip
development date and bit length A microprocessor is a computer processor for which the data processing logic and control is included on a single integrated circuit
Microprocessor
8-bit microprocessor
Semiconductor's audio processor family of chips (ATJ2085 and others) contains a Z80-compatible MCUs together with a 24-bit dedicated DSP processor. These chips
Zilog_Z80
RISC instruction set architecture
this application, two processors are wired together. The master processor (PCE negated) operates normally. The checker processor (PCE asserted) places
Motorola_88000
Micro-electronic component
processor core by definition. The Arm architecture is a common choice for SoC processor cores because some Arm-architecture cores are soft processors
System_on_a_chip
Model that describes the programmable interface of a computer processor
which is the set of processor design techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures
Instruction_set_architecture
2015 puzzle video game
processing nodes laid out in a four-by-three grid. Each node has a single processor register to store a numerical value as well as a backup register.
TIS-100
Experimental minicomputer by IBM
processing unit (CPU) design developed by IBM during the 1970s. It is considered to be the first modern RISC design, relying on processor registers for
IBM_801
architectures. See also Template:Intel processor roadmap for planned future architectures. 8086 first x86 processor; initially a temporary substitute for
List of Intel CPU microarchitectures
List_of_Intel_CPU_microarchitectures
Instruction slot being executed without the effects of a preceding instruction
that instruction is read into the processor and starts to decode, the result of the comparison is ready and the processor can now decide which instruction
Delay_slot
16-bit microprocessor
processor registers that are mapped into main memory. This allows for fast context switching, which can be accomplished by changing a single register
TMS9900
Family of RISC-based computer processors
compatible ARC-V processor IP as an extension of its ARC product line. In January 2026, Synopsys announced that it was selling its processor IP business,
ARC_(processor)
Object of a mathematical operation, quantity on which an operation is performed
the instruction, named by mnemonic, operates. The operand may be a processor register, a memory address, a literal constant, or a label. A simple example
Operand
Computer register for debugging
x86 architecture, a debug register is a register used by a processor for program debugging. There are six debug registers, named DR0...DR7, with DR4
X86_debug_register
Method of improving instruction-level parallelism
instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming
Instruction_pipelining
Topics referred to by the same term
malware can run its own code on a compromised system RCX register, a 64-bit processor register of x86 CPUs Rally Championship Xtreme Retrocommissioning
RCX
PROCESSOR REGISTER
PROCESSOR REGISTER
Boy/Male
Hindu, Indian, Malayalam, Marathi, Punjabi, Sikh
Celebratory Procession
Boy/Male
Arabic, Muslim
Method; Way; Mode; Manner; Operation; Process
Surname or Lastname
English
English : from an agent derivative of Middle English wasch(en) ‘to wash’ (Old English wæscan), hence an occupational name for a laundryman, or for someone who washed raw wool before spinning. Various other occupations, too, involved washing processes and the name may relate to any of these. For example, it may have denoted a man who washed sheep; some tenants on the manor of Burpham, near Worthing, in Sussex (where the surname is found from an early date), had as part of their feudal service to wash the flocks of their master.Americanized spelling of the German cognate Wascher.
Male
Romanian
Romanian form of Roman Latin Pompilius, possibly POMPILIU means "display, solemn procession."Â
Surname or Lastname
English
English : variant of Perrier 1 and 2.American bearers of the surname include Bennet Puryear (1826–1914), born in Mecklenburg Co., VA, youngest son of Thomas and Elizabeth (Marshall) Puryear, who studied medicine and chemistry before the Civil War, after which he became a professor of chemistry; he did pioneering work in the application of chemistry to agriculture. He had 11 children by his two wives.
Surname or Lastname
English
English : metonymic occupational name for a keeper of a lodging house, from late Old English herebeorg ‘shelter’, ‘lodging’ (from here ‘army’ + beorg ‘shelter’). (The change of -er- to -ar- is a regular phonetic process in Old French and Middle English.)Variant of French Arbour.A Harbour or Arbour, from Normandy, France, is documented in Quebec City in 1671.
Surname or Lastname
English
English : nickname from Old French certeyn ‘self-assured’, ‘determined’. (The phonetic change of -er- to -ar- was a normal process in Middle English).
Surname or Lastname
English
English : occupational name for a maker of wheels (for vehicles or for use in spinning or various other manufacturing processes), from an agent derivative of Middle English whele ‘wheel’. The name is particularly common on the Isle of Wight; on the mainland it is concentrated in the neighboring region of central southern England.A founder of Salisbury, NH, in 1634 was John Wheeler.
Surname or Lastname
English
English : occupational name from Middle English combere, an agent derivative of Old English camb ‘comb’, referring perhaps to a maker or seller of combs, or to someone who used them to prepare wool or flax for spinning. This was an alternative process to carding, and caused the wool fibers to lie more or less parallel to one another, so that the cloth produced had a hard, smooth finish without a nap.English : variant of Coomber.Probably an Americanized spelling of German Kommer or Kammer.
Biblical
judgment; process
Surname or Lastname
English (chiefly Devon)
English (chiefly Devon) : occupational name for a soapmaker, from an agent derivative of Middle English sÅpe ‘soap’ (apparently of Celtic origin). The process involved boiling oil or fat together with potash or soda.
Boy/Male
British, Christian, English, Italian
Solemn Procession; Display
Male
English
English form of Roman Latin Pompeius, possibly POMPEY means "display, solemn procession."Â
Surname or Lastname
French
French : from Old Norman French cardon ‘thistle’ (a diminutive of carde, from Latin carduus), hence a topographic name for someone who lived on land overgrown with thistles, an occupational name for someone who carded wool (originally a process carried out with thistles and teasels), or perhaps a nickname for a prickly and unapproachable person.French : possibly from a reduced form of the personal name Ricardon, a pet form of Richard.English : variant spelling of Carden, cognate with 1.
Surname or Lastname
English
English : perhaps from Middle English, Old French registre ‘register’, ‘book for recording enactments’, hence perhaps a metonymic occupational name for a scribe or clerk.
Surname or Lastname
English (West Yorkshire)
English (West Yorkshire) : habitational name from a place in Ribblesdale, North Yorkshire, recorded in Domesday Book as Winchelesuuorde, from the genitive case of the Old English byname Wincel meaning ‘child’ + Old English worð ‘enclosure’.Michael Wigglesworth (1631–1705), Puritan poet and preacher, was brought from Yorkshire to New England as a child in 1638. His first home was in Charlestown, MA; subsequently, he settled in New Haven, CT. From 1651 onward he was a fellow of Harvard College; in 1654 he was appointed minister at Malden, MA. His son and grandson, both named Edward were professors of divinity at Harvard.
Surname or Lastname
English (chiefly West Midlands)
English (chiefly West Midlands) : metonymic occupational name for a fuller, from Middle English tred(en) ‘to tread’ + well ‘well’. Fulling was the process by which newly woven cloth was cleaned and shrunk by the use of heat, water, and pressure (from treading) before finally being stretched and laid out to dry on tenter hooks.
Male
Italian
Italian form of Roman Latin Pompeius, possibly POMPEO means "display, solemn procession."Â
Surname or Lastname
English and Jewish (Ashkenazic)
English and Jewish (Ashkenazic) : occupational name for a flax grower or dealer or for someone who processed it for weaving (see Flax).Probably a respelling of German Flachsmann, of the same meaning as 1, from Middle High German vlahs ‘flax’ + man ‘man’.
Surname or Lastname
English
English : of uncertain origin. It is argued by Redmonds that this surname may have developed as a variant of Stringfellow, through a process, attested in various parish records, in which the original name is first shortened and then expanded into a form different from the original; thus Stringfellow becomes Stringfell, which becomes reinterpreted as Stringfield.
PROCESSOR REGISTER
PROCESSOR REGISTER
Boy/Male
Hindu
Lord of Subramaniam
Boy/Male
Bengali, Indian
Love; Heart; Respect
Boy/Male
Tamil
Danavarsh | தநாவரà¯à®·Â
Girl/Female
Tamil
Nehasritha | நேஹாஸà¯à®°à¯€à®¤à®¾Â
Girl/Female
Arabic, Muslim
High Price Stone
Girl/Female
Indian, Tamil
Smartness
Boy/Male
Greek Hungarian Slavic
Defender of man.
Boy/Male
Tamil
Fame
Male
French
French name derived from Latin Adrianus, ADRIEN means "from Hadria."
Boy/Male
Indian, Tamil
Son Lord Brahma; Vishnu
PROCESSOR REGISTER
PROCESSOR REGISTER
PROCESSOR REGISTER
PROCESSOR REGISTER
PROCESSOR REGISTER
v. i.
To march in procession.
n.
One who professed, or makes open declaration of, his sentiments or opinions; especially, one who makes a public avowal of his belief in the Scriptures and his faith in Christ, and thus unites himself to the visible church.
n.
A predecessor.
a.
Causing, or giving rise to, pressure or to an increase of pressure; as, pressor nerve fibers, stimulation of which excites the vasomotor center, thus causing a stronger contraction of the arteries and consequently an increase of the arterial blood pressure; -- opposed to depressor.
v. t.
To ascertain, mark, and establish the boundary lines of, as lands.
n.
The act of proceeding, moving on, advancing, or issuing; regular, orderly, or ceremonious progress; continuous course.
n.
One who professed, or publicly teaches, any science or branch of learning; especially, an officer in a university, college, or other seminary, whose business it is to read lectures, or instruct students, in a particular branch of learning; as a professor of theology, of botany, of mathematics, or of political economy.
a.
Of or pertaining to a professor; professorial.
n.
Any marked prominence or projecting part, especially of a bone; anapophysis.
n.
A division into fingers or fingerlike processes; also, a fingerlike process.
v. i.
To honor with a procession.
n.
A statement of events; a narrative.
n.
The act of proceeding; continued forward movement; procedure; progress; advance.
n.
The whole course of proceedings in a cause real or personal, civil or criminal, from the beginning to the end of the suit; strictly, the means used for bringing the defendant into court to answer to the action; -- a generic term for writs of the class called judicial.
n.
An orderly and ceremonial progress of persons, either from the sacristy to the choir, or from the choir around the church, within or without.
n.
An old term for litanies which were said in procession and not kneeling.
n.
A series of actions, motions, or occurrences; progressive act or transaction; continuous operation; normal or actual course or procedure; regular proceeding; as, the process of vegetation or decomposition; a chemical process; processes of nature.
n.
That which is moving onward in an orderly, stately, or solemn manner; a train of persons advancing in order; a ceremonious train; a retinue; as, a procession of mourners; the Lord Mayor's procession.